Dropped MMX support
Was useful a decade ago but now profiling shows it's actually slower than just plain compiler-optimized code so the extra maintenance cost is not justified.
This commit is contained in:
Duilio Protti
parent
c165721f5f
commit
ec804c0f57
36
configure.ac
36
configure.ac
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@ -52,46 +52,10 @@ AC_C_CONST
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AC_C_INLINE
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AC_C_BIGENDIAN(AC_MSG_WARN([*** You have a big endian system, Infinity have not been tested on these systems]),,)
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AC_CHECK_SIZEOF(long long)
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if test x$ac_cv_sizeof_long_long = x8; then
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:
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else
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AC_MSG_ERROR([
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*** Infinity requires a 64 bit long long type. You might want to consider
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*** using the GNU C compiler.
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])
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fi
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AC_CHECK_SIZEOF([size_t])
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AC_MSG_CHECKING([whether compiler is 32 or 64 bit])
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if test x$ac_cv_sizeof_size_t = x8; then
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AC_MSG_RESULT([64])
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compiler_width=64
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else
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AC_MSG_RESULT([32])
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compiler_width=32
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fi
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# Check for library functions.
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AC_CHECK_FUNCS([floor sqrt])
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# Arguments to specify certain features.
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AC_ARG_ENABLE([mmx],
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AS_HELP_STRING([--enable-mmx],[use MMX if available and if building with a 32 bit compiler @<:@default=enabled@:>@]),
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[mmx=$enableval],
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[mmx=yes])
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AC_MSG_CHECKING([whether to enable MMX])
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if test x$mmx = xyes; then
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if test x$compiler_width = x32; then
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AC_MSG_RESULT([yes])
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AC_DEFINE([MMX_DETECTION], [1], [Activate MMX Extensions support])
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else
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AC_MSG_RESULT([no, was requested but feature is not supported with a 64bit compiler])
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fi
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else
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AC_MSG_RESULT([no])
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fi
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AC_ARG_ENABLE([debug],
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AS_HELP_STRING([--enable-debug],[turn on debug mode @<:@default=disabled@:>@]),
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[debug=$enableval],
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@ -20,8 +20,7 @@ libinfinity_la_SOURCES = \
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compute.c compute.h \
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display.c display.h \
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effects.c effects.h \
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cputest.c cputest.h \
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mmx.h music-player.h types.h
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music-player.h types.h
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libinfinite_la_SOURCES = audacious.cc
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libinfinite_la_LDFLAGS = ${CXX}
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@ -19,9 +19,6 @@
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#include "compute.h"
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#include "config.h"
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#include "types.h"
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#ifdef MMX_DETECTION
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#include "mmx.h"
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#endif
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typedef struct t_coord {
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gint32 x, y;
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@ -274,48 +271,3 @@ inline byte *compute_surface(t_interpol *vector, gint32 width, gint32 height)
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return surface1;
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}
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#if MMX_DETECTION
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inline byte *compute_surface_mmx(t_interpol *vector, gint32 width, gint32 height)
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{
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/*@unused@*/
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volatile mmx_t mm0, mm1, mm2;
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volatile mmx_t offsets, r;
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t_interpol *interpol;
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gint32 i, j, color;
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gint32 add_dest = 0;
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guint32 add_src;
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register byte *ptr_pix;
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byte *ptr_swap;
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for (j = 0; j < height; ++j)
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for (i = 0; i < width; ++i) {
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interpol = &vector[add_dest];
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add_src = (interpol->coord & 0xFFFF) * width + (interpol->coord >> 16);
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ptr_pix = &((byte *)surface1)[add_src];
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((guint16 *)&offsets)[0] = (guint16) * (ptr_pix + width + 1);
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((guint16 *)&offsets)[1] = (guint16) * (ptr_pix + width);
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((guint16 *)&offsets)[2] = (guint16) * (ptr_pix + 1);
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((guint16 *)&offsets)[3] = (guint16) * (ptr_pix);
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/* MMX mode entry */
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movd_m2r(interpol->weight, mm1);
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movq_m2r(offsets, mm2);
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pxor_r2r(mm0, mm0);
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punpcklbw_r2r(mm0, mm1);
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pmaddwd_r2r(mm1, mm2);
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movq_r2m(mm2, r);
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emms();
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/* MMX mode exit */
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color = (((gint32 *)&r)[0] + ((gint32 *)&r)[1]) >> 8;
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if (color > 255)
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surface2[add_dest] = 255;
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else
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surface2[add_dest] = (byte)color;
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++add_dest;
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}
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ptr_swap = surface1;
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surface1 = surface2;
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surface2 = ptr_swap;
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return surface1;
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}
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#endif /* MMX_DETECTION */
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@ -73,6 +73,5 @@ void compute_resize(gint32 width, gint32 height);
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void compute_generate_vector_field(vector_field_t *vector_field);
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byte *compute_surface(t_interpol *vector, gint32 width, gint32 height);
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byte *compute_surface_mmx(t_interpol *vector, gint32 width, gint32 height);
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#endif /* __INFINITY_COMPUTE__ */
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181
src/cputest.c
181
src/cputest.c
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@ -1,181 +0,0 @@
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#include "config.h"
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#include "cputest.h"
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#include "glib.h"
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// This code is 32-bit only
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/* ebx saving is necessary for PIC. gcc seems unable to see it alone */
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#if MMX_DETECTION
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#define cpuid(index, eax, ebx, ecx, edx) \
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__asm __volatile \
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("movl %%ebx, %%esi\n\t" \
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"cpuid\n\t" \
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"xchgl %%ebx, %%esi" \
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: "=a" (eax), "=S" (ebx), \
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"=c" (ecx), "=d" (edx) \
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: "0" (index));
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#endif
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/* Function to test if multimedia instructions are supported... */
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int mm_support(void)
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{
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#if MMX_DETECTION
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int rval;
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int eax, ebx, ecx, edx;
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__asm__ __volatile__ (
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/* See if CPUID instruction is supported ... */
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/* ... Get copies of EFLAGS into eax and ecx */
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"pushf\n\t"
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"popl %0\n\t"
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"movl %0, %1\n\t"
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/* ... Toggle the ID bit in one copy and store */
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/* to the EFLAGS reg */
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"xorl $0x200000, %0\n\t"
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"push %0\n\t"
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"popf\n\t"
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/* ... Get the (hopefully modified) EFLAGS */
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"pushf\n\t"
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"popl %0\n\t"
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: "=a" (eax), "=c" (ecx)
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:
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: "cc"
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);
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if (eax == ecx)
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return 0; /* CPUID not supported */
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cpuid(0, eax, ebx, ecx, edx);
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if (ebx == 0x756e6547 &&
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edx == 0x49656e69 &&
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ecx == 0x6c65746e) {
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/* intel */
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inteltest:
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cpuid(1, eax, ebx, ecx, edx);
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if ((edx & 0x00800000) == 0)
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return 0;
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rval = MM_MMX;
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if (edx & 0x02000000)
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rval |= MM_MMXEXT | MM_SSE;
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if (edx & 0x04000000)
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rval |= MM_SSE2;
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return rval;
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} else if (ebx == 0x68747541 &&
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edx == 0x69746e65 &&
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ecx == 0x444d4163) {
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/* AMD */
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cpuid(0x80000000, eax, ebx, ecx, edx);
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if ((guint32)eax < 0x80000001)
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goto inteltest;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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if ((edx & 0x00800000) == 0)
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return 0;
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rval = MM_MMX;
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if (edx & 0x80000000)
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rval |= MM_3DNOW;
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if (edx & 0x00400000)
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rval |= MM_MMXEXT;
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return rval;
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} else if (ebx == 0x746e6543 &&
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edx == 0x48727561 &&
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ecx == 0x736c7561) { /* "CentaurHauls" */
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/* VIA C3 */
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cpuid(0x80000000, eax, ebx, ecx, edx);
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if ((guint32)eax < 0x80000001)
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goto inteltest;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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rval = 0;
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if (edx & (1 << 31))
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rval |= MM_3DNOW;
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if (edx & (1 << 23))
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rval |= MM_MMX;
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if (edx & (1 << 24))
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rval |= MM_MMXEXT;
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return rval;
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} else if (ebx == 0x69727943 &&
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edx == 0x736e4978 &&
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ecx == 0x64616574) {
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/* Cyrix Section */
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/* See if extended CPUID level 80000001 is supported */
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/* The value of CPUID/80000001 for the 6x86MX is undefined
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* according to the Cyrix CPU Detection Guide (Preliminary
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* Rev. 1.01 table 1), so we'll check the value of eax for
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* CPUID/0 to see if standard CPUID level 2 is supported.
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* According to the table, the only CPU which supports level
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* 2 is also the only one which supports extended CPUID levels.
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*/
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if (eax != 2)
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goto inteltest;
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cpuid(0x80000001, eax, ebx, ecx, edx);
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if ((eax & 0x00800000) == 0)
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return 0;
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rval = MM_MMX;
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if (eax & 0x01000000)
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rval |= MM_MMXEXT;
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return rval;
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} else {
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return 0;
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}
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#else /* not MMX_DETECTION */
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return 0;
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#endif
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}
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int mm_support_check_and_show()
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{
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int r;
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gchar *msg, *tmp;
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r = mm_support();
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if (r & 0) {
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g_message("Infinity: There is not MMX support\n");
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return r;
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}
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msg = g_strdup("Infinity: Looking for Multimedia Extensions Support...");
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if (r & MM_MMX) {
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tmp = g_strconcat(msg, " MMX", NULL);
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g_free(msg);
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msg = tmp;
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}
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if (r & MM_3DNOW) {
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tmp = g_strconcat(msg, " 3DNOW", NULL);
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g_free(msg);
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msg = tmp;
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}
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if (r & MM_MMXEXT) {
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tmp = g_strconcat(msg, " MMX2", NULL);
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g_free(msg);
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msg = tmp;
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}
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/*
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* for now this extensions are not used
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* if (r & MM_SSE) {
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* tmp = g_strconcat (msg, " SSE", 0);
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* g_free (msg);
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* msg = tmp;
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* }
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* if (r & MM_SSE2) {
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* tmp = g_strconcat (msg, " SSE2", 0);
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* g_free (msg);
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* msg = tmp;
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* }
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*/
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tmp = g_strconcat(msg, " detected", NULL);
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g_free(msg);
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msg = tmp;
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g_message("%s", msg);
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g_free(msg);
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return r;
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}
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int mmx_ok(void)
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{
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return mm_support() & 0x1;
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}
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@ -1,29 +0,0 @@
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/*
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* Cpu detection code, extracted from mmx.h ((c)1997-99 by H. Dietz
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* and R. Fisher). Converted to C and improved by Fabrice Bellard
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*/
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#ifndef _CPUTEST_H_
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#define _CPUTEST_H_
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#define MM_MMX 0x0001 /* standard MMX */
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#define MM_3DNOW 0x0004 /* AMD 3DNOW */
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#define MM_MMXEXT 0x0002 /* SSE integer functions or AMD MMX ext */
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#define MM_SSE 0x0008 /* SSE functions */
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#define MM_SSE2 0x0010 /* PIV SSE2 functions */
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/* should be defined by architectures supporting
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* one or more MultiMedia extension */
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int mm_support(void);
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/* return the result of mm_support and show the results
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* to stdout */
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int mm_support_check_and_show(void);
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/* test if mmx instructions are supported...
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* returns 1 if MMX instructions are supported, 0 otherwise */
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int mmx_ok(void);
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extern unsigned int mm_flags;
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#endif /* _CPUTEST_H_ */
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@ -313,15 +313,6 @@ inline void display_blur(guint32 vector_index)
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display_surface();
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}
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#if MMX_DETECTION
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inline void display_blur_mmx(guint32 vector_index)
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{
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surface1 = compute_surface_mmx(&(vector_field->vector[vector_index]),
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vector_field->width, vector_field->height);
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display_surface();
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}
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#endif
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void spectral(t_effect *current_effect)
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{
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gint32 i, halfheight, halfwidth;
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@ -72,7 +72,6 @@ void display_show(void);
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void change_color(gint32 old_p, gint32 p, gint32 w);
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void display_blur(guint32 vector_index);
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void display_blur_mmx(guint32 vector_index);
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void spectral(t_effect *current_effect);
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void curve(t_effect *current_effect);
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@ -27,10 +27,6 @@
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#include "infinity.h"
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#include "types.h"
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#if MMX_DETECTION
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#include "cputest.h"
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#endif
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#define wrap(a) (a < 0 ? 0 : (a > 255 ? 255 : a))
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#define next_effect() (t_last_effect++)
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#define next_color() (t_last_color++)
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@ -313,15 +309,11 @@ static int renderer(void *arg)
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gint32 frame_length;
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gint32 fps, new_fps;
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gint32 t_between_effects, t_between_colors;
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gint32 has_mmx = 0;
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fps = params->get_max_fps();
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frame_length = calculate_frame_length_usecs(fps, __LINE__);
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t_between_effects = params->get_effect_interval();
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t_between_colors = params->get_color_interval();
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#if MMX_DETECTION
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has_mmx = mm_support_check_and_show();
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#endif
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initializing = FALSE;
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for (;; ) { /* ever... */
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if (!visible) {
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@ -347,9 +339,6 @@ static int renderer(void *arg)
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G_UNLOCK(resizing);
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}
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t_begin = g_get_monotonic_time();
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if (has_mmx)
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display_blur_mmx(width * height * current_effect.num_effect);
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else
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display_blur(width * height * current_effect.num_effect);
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spectral(¤t_effect);
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curve(¤t_effect);
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|
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537
src/mmx.h
537
src/mmx.h
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@ -1,537 +0,0 @@
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/* mmx.h
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*
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* MultiMedia eXtensions GCC interface library for IA32.
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*
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* To use this library, simply include this header file
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* and compile with GCC. You MUST have inlining enabled
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* in order for mmx_ok() to work; this can be done by
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* simply using -O on the GCC command line.
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*
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* Compiling with -DMMX_TRACE will cause detailed trace
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* output to be sent to stderr for each mmx operation.
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* This adds lots of code, and obviously slows execution to
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* a crawl, but can be very useful for debugging.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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* LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR ANY PARTICULAR PURPOSE.
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*
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* 1997-99 by H. Dietz and R. Fisher
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*
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* Notes:
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* It appears that the latest gas has the pand problem fixed, therefore
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* I'll undefine BROKEN_PAND by default.
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*/
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#ifndef _MMX_H_
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#define _MMX_H_
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/* Warning: at this writing, the version of GAS packaged
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* with most Linux distributions does not handle the
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* parallel AND operation mnemonic correctly. If the
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* symbol BROKEN_PAND is defined, a slower alternative
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* coding will be used. If execution of mmxtest results
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* in an illegal instruction fault, define this symbol.
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*/
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#undef BROKEN_PAND
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/* The type of an value that fits in an MMX register
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* (note that long long constant values MUST be suffixed
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* by LL and unsigned long long values by ULL, lest
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* they be truncated by the compiler)
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*/
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typedef union {
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gint64 q; /* Quadword (64-bit) value */
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guint64 uq; /* Unsigned Quadword */
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gint32 d[2]; /* 2 Doubleword (32-bit) values */
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guint32 ud[2]; /* 2 Unsigned Doubleword */
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gint16 w[4]; /* 4 Word (16-bit) values */
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||||
guint16 uw[4]; /* 4 Unsigned Word */
|
||||
gchar b[8]; /* 8 Byte (8-bit) values */
|
||||
guchar ub[8]; /* 8 Unsigned Byte */
|
||||
gfloat s[2]; /* Single-precision (32-bit) value */
|
||||
} __attribute__ ((aligned(8))) mmx_t; /* On an 8-byte (64-bit) boundary */
|
||||
|
||||
|
||||
|
||||
/* Helper functions for the instruction macros that follow...
|
||||
* (note that memory-to-register, m2r, instructions are nearly
|
||||
* as efficient as register-to-register, r2r, instructions;
|
||||
* however, memory-to-memory instructions are really simulated
|
||||
* as a convenience, and are only 1/3 as efficient)
|
||||
*/
|
||||
#ifdef MMX_TRACE
|
||||
|
||||
/* Include the stuff for printing a trace to stderr...
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#define mmx_i2r(op, imm, reg) \
|
||||
{ \
|
||||
mmx_t mmx_trace; \
|
||||
mmx_trace.uq = (imm); \
|
||||
printf(#op "_i2r(" #imm "=0x%08x%08x, ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ ("movq %%" #reg ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#reg "=0x%08x%08x) => ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ (#op " %0, %%" #reg \
|
||||
: /* nothing */ \
|
||||
: "X" (imm)); \
|
||||
__asm__ __volatile__ ("movq %%" #reg ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#reg "=0x%08x%08x\n", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
}
|
||||
|
||||
#define mmx_m2r(op, mem, reg) \
|
||||
{ \
|
||||
mmx_t mmx_trace; \
|
||||
mmx_trace = (mem); \
|
||||
printf(#op "_m2r(" #mem "=0x%08x%08x, ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ ("movq %%" #reg ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#reg "=0x%08x%08x) => ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ (#op " %0, %%" #reg \
|
||||
: /* nothing */ \
|
||||
: "X" (mem)); \
|
||||
__asm__ __volatile__ ("movq %%" #reg ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#reg "=0x%08x%08x\n", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
}
|
||||
|
||||
#define mmx_r2m(op, reg, mem) \
|
||||
{ \
|
||||
mmx_t mmx_trace; \
|
||||
__asm__ __volatile__ ("movq %%" #reg ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#op "_r2m(" #reg "=0x%08x%08x, ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
mmx_trace = (mem); \
|
||||
printf(#mem "=0x%08x%08x) => ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ (#op " %%" #reg ", %0" \
|
||||
: "=X" (mem) \
|
||||
: /* nothing */); \
|
||||
mmx_trace = (mem); \
|
||||
printf(#mem "=0x%08x%08x\n", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
}
|
||||
|
||||
#define mmx_r2r(op, regs, regd) \
|
||||
{ \
|
||||
mmx_t mmx_trace; \
|
||||
__asm__ __volatile__ ("movq %%" #regs ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#op "_r2r(" #regs "=0x%08x%08x, ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ ("movq %%" #regd ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#regd "=0x%08x%08x) => ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ (#op " %" #regs ", %" #regd); \
|
||||
__asm__ __volatile__ ("movq %%" #regd ", %0" \
|
||||
: "=X" (mmx_trace) \
|
||||
: /* nothing */); \
|
||||
printf(#regd "=0x%08x%08x\n", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
}
|
||||
|
||||
#define mmx_m2m(op, mems, memd) \
|
||||
{ \
|
||||
mmx_t mmx_trace; \
|
||||
mmx_trace = (mems); \
|
||||
printf(#op "_m2m(" #mems "=0x%08x%08x, ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
mmx_trace = (memd); \
|
||||
printf(#memd "=0x%08x%08x) => ", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
|
||||
#op " %1, %%mm0\n\t" \
|
||||
"movq %%mm0, %0" \
|
||||
: "=X" (memd) \
|
||||
: "X" (mems)); \
|
||||
mmx_trace = (memd); \
|
||||
printf(#memd "=0x%08x%08x\n", \
|
||||
mmx_trace.d[1], mmx_trace.d[0]); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/* These macros are a lot simpler without the tracing...
|
||||
*/
|
||||
|
||||
#define mmx_i2r(op, imm, reg) \
|
||||
__asm__ __volatile__ (#op " %0, %%" #reg \
|
||||
: /* nothing */ \
|
||||
: "X" (imm))
|
||||
|
||||
#define mmx_m2r(op, mem, reg) \
|
||||
__asm__ __volatile__ (#op " %0, %%" #reg \
|
||||
: /* nothing */ \
|
||||
: "X" (mem))
|
||||
|
||||
#define mmx_r2m(op, reg, mem) \
|
||||
__asm__ __volatile__ (#op " %%" #reg ", %0" \
|
||||
: "=X" (mem) \
|
||||
: /* nothing */)
|
||||
|
||||
#define mmx_r2r(op, regs, regd) \
|
||||
__asm__ __volatile__ (#op " %" #regs ", %" #regd)
|
||||
|
||||
#define mmx_m2m(op, mems, memd) \
|
||||
__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
|
||||
#op " %1, %%mm0\n\t" \
|
||||
"movq %%mm0, %0" \
|
||||
: "=X" (memd) \
|
||||
: "X" (mems))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* 1x64 MOVe Quadword
|
||||
* (this is both a load and a store...
|
||||
* in fact, it is the only way to store)
|
||||
*/
|
||||
#define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
|
||||
#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
|
||||
#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
|
||||
#define movq(vars, vard) \
|
||||
__asm__ __volatile__ ("movq %1, %%mm0\n\t" \
|
||||
"movq %%mm0, %0" \
|
||||
: "=X" (vard) \
|
||||
: "X" (vars))
|
||||
|
||||
|
||||
/* 1x32 MOVe Doubleword
|
||||
* (like movq, this is both load and store...
|
||||
* but is most useful for moving things between
|
||||
* mmx registers and ordinary registers)
|
||||
*/
|
||||
#define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
|
||||
#define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
|
||||
#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
|
||||
#define movd(vars, vard) \
|
||||
__asm__ __volatile__ ("movd %1, %%mm0\n\t" \
|
||||
"movd %%mm0, %0" \
|
||||
: "=X" (vard) \
|
||||
: "X" (vars))
|
||||
|
||||
|
||||
/* 2x32, 4x16, and 8x8 Parallel ADDs
|
||||
*/
|
||||
#define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
|
||||
#define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
|
||||
#define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
|
||||
|
||||
#define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
|
||||
#define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
|
||||
#define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
|
||||
|
||||
#define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
|
||||
#define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
|
||||
#define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
|
||||
|
||||
|
||||
/* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
|
||||
*/
|
||||
#define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
|
||||
#define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
|
||||
#define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
|
||||
|
||||
#define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
|
||||
#define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
|
||||
#define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
|
||||
|
||||
|
||||
/* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
|
||||
*/
|
||||
#define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
|
||||
#define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
|
||||
#define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
|
||||
|
||||
#define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
|
||||
#define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
|
||||
#define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
|
||||
|
||||
|
||||
/* 2x32, 4x16, and 8x8 Parallel SUBs
|
||||
*/
|
||||
#define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
|
||||
#define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
|
||||
#define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
|
||||
|
||||
#define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
|
||||
#define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
|
||||
#define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
|
||||
|
||||
#define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
|
||||
#define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
|
||||
#define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
|
||||
|
||||
|
||||
/* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
|
||||
*/
|
||||
#define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
|
||||
#define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
|
||||
#define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
|
||||
|
||||
#define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
|
||||
#define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
|
||||
#define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
|
||||
|
||||
|
||||
/* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
|
||||
*/
|
||||
#define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
|
||||
#define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
|
||||
#define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
|
||||
|
||||
#define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
|
||||
#define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
|
||||
#define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
|
||||
|
||||
|
||||
/* 4x16 Parallel MULs giving Low 4x16 portions of results
|
||||
*/
|
||||
#define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
|
||||
#define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
|
||||
#define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
|
||||
|
||||
|
||||
/* 4x16 Parallel MULs giving High 4x16 portions of results
|
||||
*/
|
||||
#define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
|
||||
#define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
|
||||
#define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
|
||||
|
||||
|
||||
/* 4x16->2x32 Parallel Mul-ADD
|
||||
* (muls like pmullw, then adds adjacent 16-bit fields
|
||||
* in the multiply result to make the final 2x32 result)
|
||||
*/
|
||||
#define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
|
||||
#define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
|
||||
#define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
|
||||
|
||||
|
||||
/* 1x64 bitwise AND
|
||||
*/
|
||||
#ifdef BROKEN_PAND
|
||||
#define pand_m2r(var, reg) \
|
||||
{ \
|
||||
mmx_m2r(pandn, (mmx_t)-1LL, reg); \
|
||||
mmx_m2r(pandn, var, reg); \
|
||||
}
|
||||
#define pand_r2r(regs, regd) \
|
||||
{ \
|
||||
mmx_m2r(pandn, (mmx_t)-1LL, regd); \
|
||||
mmx_r2r(pandn, regs, regd) \
|
||||
}
|
||||
#define pand(vars, vard) \
|
||||
{ \
|
||||
movq_m2r(vard, mm0); \
|
||||
mmx_m2r(pandn, (mmx_t)-1LL, mm0); \
|
||||
mmx_m2r(pandn, vars, mm0); \
|
||||
movq_r2m(mm0, vard); \
|
||||
}
|
||||
#else
|
||||
#define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
|
||||
#define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
|
||||
#define pand(vars, vard) mmx_m2m(pand, vars, vard)
|
||||
#endif
|
||||
|
||||
|
||||
/* 1x64 bitwise AND with Not the destination
|
||||
*/
|
||||
#define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
|
||||
#define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
|
||||
#define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
|
||||
|
||||
|
||||
/* 1x64 bitwise OR
|
||||
*/
|
||||
#define por_m2r(var, reg) mmx_m2r(por, var, reg)
|
||||
#define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
|
||||
#define por(vars, vard) mmx_m2m(por, vars, vard)
|
||||
|
||||
|
||||
/* 1x64 bitwise eXclusive OR
|
||||
*/
|
||||
#define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
|
||||
#define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
|
||||
#define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
|
||||
|
||||
|
||||
/* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
|
||||
* (resulting fields are either 0 or -1)
|
||||
*/
|
||||
#define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
|
||||
#define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
|
||||
#define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
|
||||
|
||||
#define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
|
||||
#define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
|
||||
#define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
|
||||
|
||||
#define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
|
||||
#define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
|
||||
#define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
|
||||
|
||||
|
||||
/* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
|
||||
* (resulting fields are either 0 or -1)
|
||||
*/
|
||||
#define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
|
||||
#define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
|
||||
#define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
|
||||
|
||||
#define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
|
||||
#define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
|
||||
#define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
|
||||
|
||||
#define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
|
||||
#define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
|
||||
#define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
|
||||
|
||||
|
||||
/* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
|
||||
*/
|
||||
#define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
|
||||
#define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
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#define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
|
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#define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
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|
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#define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
|
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#define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
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#define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
|
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#define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
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|
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#define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
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#define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
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#define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
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#define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
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|
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|
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/* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
|
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*/
|
||||
#define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
|
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#define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
|
||||
#define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
|
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#define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
|
||||
|
||||
#define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
|
||||
#define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
|
||||
#define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
|
||||
#define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
|
||||
|
||||
#define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
|
||||
#define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
|
||||
#define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
|
||||
#define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
|
||||
|
||||
|
||||
/* 2x32 and 4x16 Parallel Shift Right Arithmetic
|
||||
*/
|
||||
#define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
|
||||
#define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
|
||||
#define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
|
||||
#define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
|
||||
|
||||
#define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
|
||||
#define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
|
||||
#define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
|
||||
#define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
|
||||
|
||||
|
||||
/* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
|
||||
* (packs source and dest fields into dest in that order)
|
||||
*/
|
||||
#define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
|
||||
#define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
|
||||
#define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
|
||||
|
||||
#define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
|
||||
#define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
|
||||
#define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
|
||||
|
||||
|
||||
/* 4x16->8x8 PACK and Unsigned Saturate
|
||||
* (packs source and dest fields into dest in that order)
|
||||
*/
|
||||
#define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
|
||||
#define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
|
||||
#define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
|
||||
|
||||
|
||||
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
|
||||
* (interleaves low half of dest with low half of source
|
||||
* as padding in each result field)
|
||||
*/
|
||||
#define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
|
||||
#define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
|
||||
#define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
|
||||
|
||||
#define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
|
||||
#define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
|
||||
#define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
|
||||
|
||||
#define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
|
||||
#define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
|
||||
#define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
|
||||
|
||||
|
||||
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
|
||||
* (interleaves high half of dest with high half of source
|
||||
* as padding in each result field)
|
||||
*/
|
||||
#define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
|
||||
#define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
|
||||
#define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
|
||||
|
||||
#define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
|
||||
#define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
|
||||
#define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
|
||||
|
||||
#define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
|
||||
#define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
|
||||
#define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
|
||||
|
||||
|
||||
/* Empty MMx State
|
||||
* (used to clean-up when going from mmx to float use
|
||||
* of the registers that are shared by both; note that
|
||||
* there is no float-to-mmx operation needed, because
|
||||
* only the float tag word info is corruptible)
|
||||
*/
|
||||
#ifdef MMX_TRACE
|
||||
|
||||
#define emms() \
|
||||
{ \
|
||||
printf("emms()\n"); \
|
||||
__asm__ __volatile__ ("emms"); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define emms() __asm__ __volatile__ ("emms")
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _MMX_H_ */
|
||||
Loading…
Reference in New Issue